In various electronic systems it is desirable to provide stable, known output voltage states during transition period when one or more voltages to be monitored have not yet reached a stable operating voltage. For example, in electronic postage meter systems of the type disclosed in U.S. Pat. No. 3,978,457 for Microcomputerized Electronic Postage Meter Systems, U.S. Pat. No. 3,938,095 for Computer Responsive Postage Meter, European Patent Application No. 80400603.9, filed May 5, 1980, for Electronic Postage Meter Having Improved Security and Fault Tolerance Features, U.S. Pat. No. 4,301,507 for Electronic Postage Meter Having Plural Computing Systems, and copending application Ser. No. 447,815, filed Dec. 8, 1982, for Stand-Alone Electronic Mailing Machine, one or more microprocessors are employed with some form of non-volatile memory (NVM) capability to store critical postage accounting information. This information includes, for example, the amount of postage remaining in the meter for subsequent printing and the total amount of postage already printed by the meter. Other types of accounting or operating data may also be stored in the non-volatile memory, as desired.
However, during the power-up and power-down cycles of an electronic postage meter, the microprocessor and other devices in the meter may be non-operational, unstable or function erratically until the voltages to be monitored, e.g., chip supply voltages, reach stable levels. Such erratic operation may result in the erasure of data or the writing of spurious data in NVM prior to reaching a known operational voltage during power-up and subsequent to falling below the known operational voltage during power-down of the meter.